@article {CTA:CTA829,
	title = {A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning},
	journal = {International Journal of Circuit Theory and Applications},
	volume = {41},
	number = {9},
	year = {2013},
	pages = {904{\textendash}923},
	abstract = {Floorplanning is a vital phase in the design process of Very Large Scale Integrated (VLSI) circuit physical design process. The main objective of floorplanning is to minimize the area and wire length with the fixed-outline constraints. Most of the tools developed so for are using weighted some approach. Hence, these tools suffer from weights assignment and undesirable bias toward particular objective. A tailor-made multiobjective optimization tool could overcome this issue.In this article, we propose a new multiobjective optimization technique named self adaptive B*tree coded Archived Multiobjective Simulated Annealing Algorithm (AMOSA) and implemented to solve the VLSI nonslicing floorplanning problem. The proposed model provides choices from among different trade-off solutions. The self adaptive B*tree coded AMOSA combines the novel cooling schedule, B*tree encoding, improved neighborhood search procedure, self adaptive local search, and the AMOSA. In B*tree coded AMOSA, the solution is represented using a B*tree. This representation causes a reduction in time and space complexity of AMOSA. The B*tree coded AMOSA is further improved with a novel cooling schedule, a self adaptive local search mechanism, and an improved neighborhood search procedure, resulting in further reduction of computational time and improvement in exploration capability. The FastSA, B*tree coded AMOSA, and the self adaptive B*tree coded AMOSA are tested with Microelectronics Center of North Carolina (MCNC) benchmarks. The results are compared and validated. The proposed method shows 59.8\% improvement in the computational time for ami49 without changing the system quality. Copyright {\textcopyright} 2012 John Wiley \& Sons, Ltd.},
	keywords = {AMOSA, Floorplanning, Multiobjective optimization, Simulated annealing algorithm, VLSI layout CAD},
	issn = {1097-007X},
	doi = {10.1002/cta.829},
	url = {http://dx.doi.org/10.1002/cta.829},
	author = {Anand, S. and Saravanasankar, S. and Subbaraj, P.}
}
