@conference {3609,
	title = {An ASIC design of an optimized multiplication using twin precision},
	booktitle = {2017 International Conference on Intelligent Computing and Control Systems (ICICCS)2017 International Conference on Intelligent Computing and Control Systems (ICICCS)},
	year = {2017},
	month = {15-16 June 2017},
	pages = {455 - 461},
	abstract = {A binary multiplier is an electronic circuit used in digital electronics, such as computer, to multiply two binary numbers. A binary computer does exactly the same, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1) and that{\textquoteright}s much easier than in decimal, as the product by 0 or 1 is just 0 or same number. Therefore the multiplication of two binary numbers comes down to the process of calculating the partial products(which are 0 or the first number), shifting them left and the adding them together. Twin precision can be efficiently used to attain double output in multipliers and this method is simulated in signed multipliers. Twin precision is defined as one of the coherent method to attain double throughput in the multipliers. Twin precision is implemented using Modified Booth multiplier. The added advantage of reduced partial product is the reason for using Modified Booth multiplier. The possibility of combining N \& N/2 bit multiplication in the same N bit tree multiplier is called as TP multiplier, where N is the bit of the multiplier. Since the partial product generation of MB multiplication is based on the encoding and decoding logic, it is not possible to use the results of full precision(N bit) for narrow width(N/2 bit) MB multiplication. Therefore MB algorithm reduces N number of partial product rows to N/2 rows. Multiplexers are needed to select the approximate partial products for N and N/2 multiplications. When more number of multiplexers are used area increases. Here in this paper, TP implementation it is done using an extra logic block for obtaining double throughput. Optimized TP multiplier gave a way for overall reduction in power, delay \& area. This is then implemented in floating point multiplication and is taken as application study. It is observed that the speed of the floating point multiplier to genrate product is found faster than the present multipliers. Simulations and evaluations are done- in Cadence RTL compiler using TSMC 90nm library.},
	keywords = {application specific integrated circuits, ASIC, ASIC design, binary computer, binary encoding, binary multiplier, binary numbers, bit tree multiplier, Control systems, Delays, digital electronics, Electronic mail, Encoding, Floating Point, floating point arithmetic, Hardware, IEEE 754, integrated circuit design, logic design, MB multiplication, Modified Booth, modified booth multiplier, Multiplexing, multiplying circuits, optimized multiplication, optimized TP multiplier, partial product generation, partial product rows, point multiplication, reduced partial product, RTL compiler, signed multipliers, size 90.0 nm, Throughput, TSMC library, twin precision, word length 2.0 bit},
	author = {A. S. Abraham and Anand, S.}
}
