@conference {5631,
	title = {Study and Implementation of Ethernet Based Synchronization in Distributed Data Acquisition System},
	booktitle = {International Conference on Computer Networks and Inventive Communication Technologies},
	year = {2019},
	pages = {416-423},
	publisher = {Springer, Cham},
	organization = {Springer, Cham},
	author = {JS Manjaly, AK Krishnan, PL Bonifus}
}
@conference {5338,
	title = {Vehicle To Vehicle Communication Based Collision Warning Algorithm For Overtaking Assistance},
	booktitle = {International Conference on Recent Trends in Computational Engineering \& Technologies (ICRTCET{\textquoteright}18)},
	year = {2018},
	month = {17-18 May 2018},
	pages = {292-302},
	publisher = {Global Journal of Engineering Science and Researches},
	organization = {Global Journal of Engineering Science and Researches},
	address = {Bengaluru},
	author = {Jafis P C and Bonifus PL}
}
@conference {5335,
	title = {An efficient built-in self-repair scheme for multiple RAMs},
	booktitle = {2017 2nd IEEE International Conference on Recent Trends in Electronics, Information \& Communication Technology (RTEICT)},
	year = {2017},
	month = {19-20 May 2017},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Bangalore},
	author = {Arathy S Nair and Bonifus PL}
}
@article {5337,
	title = {Design and Analysis of Modified Fast Compressors for MAC Unit},
	journal = {International Journal of Computer Trends and Technology (IJCTT)},
	volume = {36},
	year = {2016},
	pages = {213-218},
	author = {Anusree T U and Bonifus PL}
}
@conference {2055,
	title = {Design of AES architecture with area and speed tradeoff},
	booktitle = {International Conference on Emerging Trends in Engineering, Science and Technology (ICETEST - 2015)},
	volume = {24},
	year = {2016},
	month = {9-11 Dec 2015},
	pages = {1135 {\textendash} 1140 },
	publisher = {Elsevier Procedia Technology},
	organization = {Elsevier Procedia Technology},
	edition = { Procedia Technology 24 },
	address = { Trichur},
	author = {Neenu Shaji and Bonifus P.L}
}
@article {5336,
	title = {A Study on Compressor Adders for Fast Multipliers},
	journal = {International Journal of Engineering Research \& Technology (IJERT)},
	volume = {5},
	year = {2016},
	pages = {633-635},
	author = {Anusree T U and Bonifus PL}
}
@article {2053,
	title = {Area Optimized Architecture for AES Mix Column Operation},
	journal = {International Journal of Engineering Research \& Technology (IJERT) ISSN: 2278-0181},
	volume = {4},
	year = {2015},
	pages = {663-665},
	author = {Neenu Shaji and Bonifus PL}
}
@article {2054,
	title = {Implementation of FFT Butterfly Algorithm Using SMB Recoding Techniques},
	journal = {IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) },
	volume = {5},
	year = {2015},
	pages = {60-65},
	author = {Vivek Joshy and Bonifus PL}
}
@conference {1699,
	title = {DUAL MODE LOGIC BASED ADDER FOR ENERGY EFFICIENT,HIGH PERFORMANCE CMOS STRUCTURES},
	booktitle = {First International Conference on Computational Systems and Communications (ICCSC)},
	year = {2014},
	month = {17-18 December},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Trivandrum},
	author = {Christa Mariam George and Bonifus P.L}
}
@article {535,
	title = {ECC ENCRYPTION SYSTEM USING  ENCODED MULTIPLIER AND VEDIC  MATHEMATICS},
	journal = {International Journal of Advanced Research in Electrical,  Electronics and Instrumentation Engineering},
	volume = {VOLUME 2},
	year = {2013},
	abstract = {This paper presents an efficient design and implementation of ECC Encryption System using Encoded Multiplier. ECC algorithm is implemented based on ancient Indian Vedic Mathematics. The speed of the system mainly depends on multipliers and adders. To improve the speed of the system, the multiplier architecture is modified using a new encoded algorithm. Using this algorithm number of partial products in the multiplier architecture is reduced to half and thus it speeds up the operation. Effectively no multipliers are required and number of adders required is reduced drastically. The most significant aspect of this paper is the development of encoded architecture and embedding it in Point Multiplication circuitry of ECC algorithm. The coding is done in Verilog HDL and FPGA implementation using Xilinx Spartan 6 library.},
	author = {Bonifus PL and Dani George}
}
@conference {1643,
	title = {RSA Encryption System Using Encoded Multiplier and Vedic Mathematics},
	booktitle = {International Conference on Advanced Computing and Communication Systems},
	year = {2013},
	month = {Dec. 19 {\textendash} 21},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Coimbatore},
	author = {Dani George and Bonifus PL}
}
