In digital VLSI, power dissipation has become a prime constraint. Many design architecture and techniques
have been developed to reduce power dissipation. In this paper implementation of sequential circuits such as D flip
flop, PIPO shift register and RAM in Gate diffusion input (GDI) technique and its comparison with other logic styles
is presented. This technique allows reduced power consumption and delay while maintaining low complexity of logic
design. The design is simulated using Mentor Graphics Design Architect.