Intel Corporation, Santa Clara, California, USA, April 2015 – Sept 2015  Pre SiliconVerification engineer, Data CenterGroup - Advanced memory controller products. Testplan reviews for RAS and Interrupts. Random simulations with a System Verilog/UVM based Fullchip and Subsystem test environment to improve functional coverage.

Cisco Systems, San Jose, California, USA, Feb 2013 – Sept 2014 Technical Leader Responsible for full chip verification of a Network Switch SoC, and block level verification of Flexible Lookup Unit. Performed functional coverage analysis/closure.

Applied Micro, Sunnyvale, California, USA, Mar 2011 – Feb 2013 Principal Engineer Verification lead for the Level 3 Cache of a 64 bit ARM Multicore SoC – MicroServer on a Chip.  Developed simulation environment, test plan, directed and constrained random test sequences for functional coverage closure, simulated and debugged the design.

Sun Microsystems/Oracle, Santa Clara, California, USA, Dec 2002 – Mar 2011 Principal Engineer, Microprocessor Design Verification Lead for Muti Core Multithreaded SPARC Microprocessor designs. Worked on Integer Unit, Trap & Commit Unit and Interrupts.Worked on Chip level verification of RAS (Reliability Availability Serviceability) features. Verified Interrupts and Random testing. Worked on Performance Instrumentation Hardware and Test and Debug features.

Startups: Tasman Networks, SandCraft, Silicon Spice, Sunnyvale, USA Mar 2000 – Dec 2002 Design Verification Manager, Senior Staff Engineer Worked on the development of a Network Processor at Tasman.  A MIPS Microprocessor at Sandcaft and a South Bridge/IO chip at Silicon Spice/Broadcom.

Fujitsu HAL Computer Systems, Campbell, California, USA Jan 1992 – Mar 2000 Microprocessor Development Engineer Lead/Manager. Startupcompanyacquired by Fujitsu. Worked on the development of the first 64 bit SPARC. Microprocessor (HAL R1) and Server computer. Started working as Senior Engineer and later as Technical Lead and Manager of the Design Verification team. Worked on the development of follow on Uni and Multiprocessing CPU designs and Systems. Worked on CPU Core design verification, MMU, IO Interface Unit and Floating Point Unit.

Indus Technologies/Hewlett Packard, Cupertino, California, April 1990 – Dec 1991 VLSI Design Verification Engineer

DoE CAD/VLSI project IIT Madras, Senior Scientific Officer Gr II,  April 1988 – April 1990 VLSI CAD tool development, Design and Simulation of  ASICs and Microprocessor circuits, conducting workshops.

ORG Systems Bangalore, Customer Engineer -Hardware,   April 1985 – May 1986 Installation and Maintenance of Mini and Mainframe Computers and Peripherals