Publications

In VLSI physical design, floorplanning is an important step. When there is a substantial increase in the number of modules in circuits, physical design automation tools stand in need of efficient algorithms. This paper proposes a new algorithm, namely B*tree crossover simulated annealing algorithm (BCSA), for fixed-outline floorplanning problem. This work aims to minimize dead space with the objective of optimizing area and wire length. A novel crossover in B*tree is introduced with the efficient simulated annealing algorithm. Proposed approaches improve the exploration capabilities of simple simulated annealing algorithm. BCSA is tested on famous Microelectronics Center of North Carolina benchmark circuits. Results are comparatively better than most of the state-of-the-art algorithms. BCSA produces less dead space. BCSA algorithm is found more efficient for problems of larger sizes.