Course Objective

This course is about designing and implementing digital systems by using a Hardware Description Language called Verilog . Verilog is an industry standard hardware description language that is widely used for specifying, modeling, designing and simulating digital systems.  This course emphasize on good digital design practices and verification of the designs by writing efficient test-benches. Students will gain valuable hands-on experience on writing efficient hardware designs using verilog and perform high-level HDL simulations using ModelSim /Xilinx.

 The specific objectives of this course are:

• To develop skills in modeling basic digital circuits in hardware description languages
• To use Verilog to model digital hardware circuits and to learn various modeling methods in Verilog .
• To familiarize various tools used for designing and simulating circuits described in Verilog.
• To understand various advanced modeling techniques in implementing Finite State Machines and other sequential/ combinational digital logics Verilog.
• To develop skills to work in a team for successfully completing a Verilog project and present the work in the form of a report.

Contribution to outcomes

Lectures are conducted to introduce the concept of Digital Design using Hardware Description Languages. The Verilog is explained in detail with programme examples for each and every topic. The students will write similar programmes in the their notebooks.

This will enable students to show the ability to design and specify digital systems and to define a digital system from the requirement specification and implement and verify the system in Verilog using structural, data flow and behavioral modeling techniques.

After completing a series of lectures on a particular topic, students are directed to the Lab and they are asked to write Verilog programme for small digital circuits discussed in the lecture. They are asked to write the Verilog programme, compile, simulate and analyse the programme to verify the functional logic of the particular circuit which they have implemented. XILINX ISE or Modelsimm CAD tools are used for this.

This will enable students to show ability to write test-benches and simulate digital systems described in Verilog  by using industry standard CAD tools (Xilinx ISE, Modelsim). They will show ability to analyze the behaviour of the digital systems and debug the system described in Verilog by using industry standard CAD tools (Xilinx ISE, Modelsim).