Publications

2017
John PK, P RA. BIST Architecture for Multiple RAMs in SoC. In: 7th International Conference on Advances in Computing and Communications 2017,Rajagiri School of Engineering. Vol. 115,2017. RSET,Kakkanad: Elsevier Procedia; 2017. p. 159-165.
John PK, Antony RP. Optimized BIST Architecture for Memory Cores and Logic Circuits using CLFSR. In: International Conference on Intelligent Computing, Instrumentation and Control Technologies 2017. Kannur, India: IEEE; 2017.
2015
Antony RP, Joseph AM. Design and Implementation of Double Precision Floating Point Comparator. In: 1st Global Colloquium on Recent Advancements and Effectual Researches in Engineering, Science and Technology - RAEREST 2016 . Elsevier; 2015.
2014
Surendran EKL, Rony AP. IMPLEMENTATION OF FAST MULTIPLIER USING MODIFIED RADIX-4 BOOTH ALGORITHM WITH REDUNDANT BINARY ADDER. International Conference on Computational Systems and Communications (ICCSC-2014). 2014:266-271.
Antony RP, Joseph EP. VLSI design and comparative analysis of memory BIST controllers. First International Conference on Computational Systems and Communications (ICCSC). 2014:372 - 376.
2013
Rony AP, Elina R. Implementation of Extended Open Core Protocol Interface Memory System using Verilog HDL. In: International Conference On Green Computing , Communication And Conservation Of Energy (ICGCE 2013). ; 2013.