Citation:
John PK, P RA. BIST Architecture for Multiple RAMs in SoC. In: 7th International Conference on Advances in Computing and Communications 2017,Rajagiri School of Engineering. Vol. 115,2017. RSET,Kakkanad: Elsevier Procedia; 2017. p. 159-165.
Department of Electronics and Communication
Rajagiri School of Engineering & Technology,Kochi -682 039
(email)