Optimized BIST Architecture for Memory Cores and Logic Circuits using CLFSR

Citation:

John PK, Antony RP. Optimized BIST Architecture for Memory Cores and Logic Circuits using CLFSR. In: International Conference on Intelligent Computing, Instrumentation and Control Technologies 2017. Kannur, India: IEEE; 2017.

Date Presented:

7 July

Rony Antony P

Assistant Professor

Optimized BIST Architecture for Memory Cores and Logic Circuits using CLFSR

Citation:

Date Presented:

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