Area Optimized Architecture for AES Mix Column Operation

Citation:

Shaji N, PL B. Area Optimized Architecture for AES Mix Column Operation. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181. 2015;4(09):663-665.

v4i9-ijertv4is090602.pdf569.95 KB
security, cryptography, aes, encryption, decryption, field, programmable, gate, array, (fpga), galois, field, rtl.area, optimized, architecture, aes, mix, column, operation: http://www.ijert.org/view-pdf/14101/area-optimized-architecture-for-aes-mix-column-operation