Citation:
Shaji N, P.L B. Design of AES architecture with area and speed tradeoff. In: International Conference on Emerging Trends in Engineering, Science and Technology (ICETEST - 2015). Vol. 24. Procedia Technology 24 . Trichur: Elsevier Procedia Technology; 2016. p. 1135 – 1140 .
Date Presented:
9-11 Dec 2015 | design_of_aes_architecture.pdf | 607.6 KB |
Security; Cryptography; AES; Encryption; Decryption; Field Programmable Gate Array(FPGA); RTL: http://www.sciencedirect.com/science/article/pii/S2212017316301505