This paper presents an efficient design and implementation of ECC Encryption System using Encoded Multiplier. ECC algorithm is implemented based on ancient Indian Vedic Mathematics. The speed of the system mainly depends on multipliers and adders. To improve the speed of the system, the multiplier architecture is modified using a new encoded algorithm. Using this algorithm number of partial products in the multiplier architecture is reduced to half and thus it speeds up the operation. Effectively no multipliers are required and number of adders required is reduced drastically. The most significant aspect of this paper is the development of encoded architecture and embedding it in Point Multiplication circuitry of ECC algorithm. The coding is done in Verilog HDL and FPGA implementation using Xilinx Spartan 6 library.